The present invention relates to multi-port memories, and more specifically, relates to a compact decode and multiplexing circuitry for a multi-port memory having a common memory interface.
Multi-port memories are used in a variety of applications. In one application, multi-port static random access memory (SRAM) arrays are used as memory buffers between logic circuitry and slower dynamic random access memory (DRAM). Conventionally, the SRAM arrays used in these types of applications are two-port memories having two independently accessible ports. This allows for memory locations in the SRAM to be accessed by the logic circuitry through one of the two ports in order to free the logic circuitry from having to wait to complete memory accesses to the slower DRAM, and further allows the DRAM to access the SRAM through the other port to update any data.
FIG. 1 shows a conventional multi-port memory 100 having two two-port memory arrays 102, 104 sharing a common interface, represented by address terminals 112, 113 and common data bus 114. As shown in FIG. 1, the memory arrays 102, 104 are configured as a 256xc3x978 SRAM array and a 32xc3x978 SRAM array. The memory arrays 102, 104 can be embedded SRAM arrays formed on a single die with additional logic circuitry (not shown). The two-port memory arrays 102, 104 each have one memory port 120, 130, that provides access to the respective memory arrays. Although not shown in FIG. 1, respective logic circuitry can be coupled to each port to access the memory arrays 102, 104. Each port 103, 105, 120, 130 has its own decode circuitry (not shown) to decode the memory address provided over a respective address terminal to provide access to the memory array through the respective port. The memory port 120 is represented by address terminal 122 and data input/output 124, and the memory port 130 is represented by address terminal 132 and data input/output 134. Each multi-port memory array 102, 104 also has a second memory port 103, 105 that also provides access to each memory array 102, 104. However, each data port is coupled to a multiplexer 106 to be accessed through the common memory interface 110. The common interface 110 can be coupled to DRAM so that the multi-port memory 100 can be used as a memory buffer between any logic circuitry and the DRAM. As shown in FIG. 1, the data buses 115, 116 from each of the memory arrays 102, 104 are routed to the multiplexer 106 for selection of which of the data busses 115, 116, to couple to the common data bus 114 for access. Selection of which of the data busses 115, 116 is based on a selection signal SEL0/1 provided to the multiplexer 106 through a selection terminal 108.
Several issues arise in forming multi-port memories having a common memory interface from conventional two-port memories. For example, where the multi-port memory 100 is implemented as an embedded memory, forming byte-wide data busses for each memory array consumes precious space on a semiconductor die. The problem is exacerbated for byte-wide multi-port memories having several memory ports in addition to the common memory interface 110. Additionally, as previously discussed, each port of a two-port memory has respective decode circuitry and requires a common multiplexer for coupling to a common memory interface. This circuitry further consumes space on the semiconductor die. Moreover, the number and length of conductive lines forming the multiple data busses may result in significant loading effects caused by signal line impedance and cross coupling. Another issue with the conventional multi-port memory 100, is that by including a multiplexer in the data path, such as the multiplexer 106, timing constraints for the multi-port memory are increased since propagation delays through the multiplexer 106 and the need to ensure signal integrity add to memory access times. Typically, memory access times are relaxed to accommodate any timing delays caused by the multiplexer 106. However, increasing memory access times is viewed as a very undesirable solution.
Therefore, there is a need for an alternative multiplexing scheme for a multi-port memory having a common memory interface shared by the multiple memory arrays of the multi-port memory.
According to one aspect of the invention, a memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (rxc2x7sxc2x7t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (mxc3x97t) memory array and further organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (nxc3x97t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (rxc3x97sxc3x97t) memory array.
In another aspect of the invention, a method of organizing a memory array having m memory locations for use in a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The method includes organizing the m memory locations into first and second non-overlapping memory sub-arrays. The first memory sub-array is organized as a (rxc3x97t) memory array accessible through a first of the plurality of memory ports and the second memory sub-array is organized as a (sxc3x97t) memory sub-array accessible through a second of the plurality of memory ports. The sum of (rxc2x7t) and (sxc2x7t) is equal to m, and both r and s multiples of a value q. The method further includes organizing the m memory locations into a common memory array organized as a (qxc3x97((r/q)+(s/q))xc3x97t) memory array accessible through the common memory interface.